The present invention relates to methods of making contacts for microelectronic elements, such as semiconductor wafers and chips and circuit panels, and more specifically relates to methods of making contacts on microelectronic elements that are bondable with leads using relatively low bonding forces.
Semiconductor chips are typically connected to external circuitry through electrical contacts provided on a face surface of the chip. The contacts on the chip may be disposed in various patterns such as a grid substantially covering the front surface of the chip, commonly referred to as an xe2x80x9carea array,xe2x80x9d or in elongated rows extending parallel to and adjacent each edge of the chip face surface. Each contact on the chip must be connected to external circuitry, such as the circuitry of a supporting substrate or circuit panel. Various processes for making these interconnections use prefabricated arrays of leads or discrete wires. For example, in a ball or stitch bonding process, a wire-bonding tool is used to electrically connect chip contacts with contacts on a circuit panel. After a non-contact bearing surface of the chip is mounted on the circuit panel, a fine wire is fed through the wire-bonding tool. The bonding tool is then brought into engagement with the contact on the chip so as to bond the wire to the contact. The tool is then moved to a contact on the circuit panel, so that a small piece of wire is dispensed and formed into a lead. The lead connects the chip contact with the circuit panel contact. This process is repeated for every contact on the chip.
In what is commonly referred to as the tape automated bonding or xe2x80x9cTABxe2x80x9d process, a dielectric supporting tape, such as a thin foil of polyamide is provided with an aperture slightly larger than the chip. An array of metallic leads is provided on one surface of the dielectric film. These leads extend inwardly from around the aperture towards the edges of the aperture. Each lead has an innermost end projecting inwardly, beyond the edge of the aperture. The innermost ends of the leads are arranged side by side at spacing corresponding to the spacing of the contacts on the chip. The dielectric film is juxtaposed with the chip so that the aperture is aligned with the chip and so that the innermost ends of the leads will extend over the contact bearing surface on the chip. The innermost ends of the leads are then bonded to the contacts of the chip, such as by using ultrasonic or thermocompression bonding techniques. The outer ends of the leads are connected to external circuitry.
In a xe2x80x9cbeam leadxe2x80x9d process, the chip is provided with individual leads extending from contacts on the front surface of the chip outwardly beyond the edges of the chip. The chip is positioned on a substrate with the outermost ends of the individual leads protruding over contacts on the substrate. The leads are then engaged with the contacts and bonded thereto so as to connect the contacts on the chip with contacts on the substrate.
Typically, the leads are bonded to the chip contacts by a bonding tool using heat, force, ultrasonic energy, or a combination of two or more thereof, for a given time period. If an incorrect ratio of force, heat and/or ultrasonic energy is used, the bond between the leads and the contacts may be too weak to undergo the thermal cycling stress during operation of the chip (heating and cooling cycles during operation). For example, if too much force is used the bonding tool may create areas of the lead which are prone to early fatigue during thermal cycling because of excessive non-uniform deformations in the bonding region typically causing early breaks in the lead at the point the lead bends up from the chip surface (commonly referred to as a xe2x80x9cheel breakxe2x80x9d). Further, obtaining good intermetallic bonds which are substantially uniform across the surface of the bond between the lead and contact surfaces is critical to a well performing lead bond. Uneven intermetallic growth can cause embrittlement of the lead in and around the bond area thereby causing early fatigue of the lead during thermal cycling. Intermetallic diffusion will typically only take place at the bonded sites of the lead and the contact thereby causing sites of gross intermetallic formation which may cause an unreliable bond. Further, impurities in the bond lead (such as co-deposited plated lead impurities or other surface impurities) tend to migrate to the unevenly bonded intermetallic sites during the high temperatures used in chip packaging thus weakening the bond. Both of these problems may worsen the creation of a phenomenon called Kirkendahl Voiding (voids created at the boundary of two metals having different interdiffusion coefficients). This voiding along the boundary of the two metals (lead/contact) generally causes intermetallic degradation, brittleness of the lead itself and weakening of the bond making the lead/bond susceptible to failure during thermal cycling.
As chip packages are made smaller and smaller, the lead dimensions will also be reduced compounding this problem by making it more difficult to reliably bond the leads to their respective chip contacts using conventional bonding techniques.
Commonly assigned U.S. Pat. No. 5,390,844, the disclosure of which is hereby incorporated by reference herein, discloses a bonding tool for bonding leads to contacts on semiconductor chips. In preferred embodiments, the bonding tool has a lower end defining guide surfaces for engaging elongated leads disposed beneath the tool upon downward movement of the tool from above the leads. The guide surfaces are adapted to engage a lead extending in either of two mutually orthogonal directions and to center the engaged lead beneath the bonding region of the lower end so that the lead can be engaged and bonded by the tool. With either orientation of the lead, the tool will capture and align the lead, and bring the lead into position for bonding. Commonly assigned U.S. Pat. No. 5,489,749, the disclosure of which is incorporated by reference herein, describes another bonding tool arranged to capture and align a lead. In preferred embodiments of the ""749 patent, the bonding tool is a blade-like device with an elongated bottom edge and with a groove extending lengthwise along the bottom edge for engaging the leads to be bonded.
FIGS. 1A-1E show prior art methods commonly use to bond leads to contacts on a microelectronic element. Referring to FIG. 1A, a microelectronic element 10 has a contact bearing face 12 including die pad 14 and a bump of a conductive bonding material 16, such as gold. The conductive bump 16 shown in FIG. 1A is formed using a wire bonding tool. However, other methods may be used for depositing conductive bumps 16 including using a stenciling process. Referring to FIG. 1B, the gold bump 16 is then reflowed, such as by applying heat energy to the gold bump, to allow surface tension to reshape the conductive bump 16 into one having a rounded, curved or spherical top surface.
Referring to FIG. 1C, the microelectronic element is then juxtaposed with a second element (not shown) having one or more conductive leads 18, such as gold leads. The tip ends 20 of the conductive leads are aligned with the bump 16 so that the lead 18 may be bonded to the bump 16, thereby creating an electrical interconnection between lead 18 and die pad 14.
Referring to FIGS. 1D, 2A and 2B, a bonding tool 22 is then utilized for bonding the lead 18 to the bump 16. The bonding tool 22 includes a tip end 24 having a substantially flat surface 26.
Referring to FIG. 1E, a downward force F is applied through tip end 24 of bond tool 22 and onto lead 18 for forming a bond between lead 18 and conductive bump 16. The strength of the bond is dependent upon three process factors: temperature, time and force used for forming the bond. The application of force using bond tool 22 exerts a stress in the mating surfaces of the lead 18 and bump 16 which provides the interfacial contact needed for diffusion bonding.
Despite the substantial time and effort devoted heretofore to the problems associated with providing bonding tools, there are still unmet needs for improvements in such semiconductor chip package structures and methods.
The present invention provides methods of making bondable contacts on a microelectronic element. In one preferred embodiment, the method includes providing a microelectronic element having one or more die pads on a first face thereof and depositing conductive bonding material, such as gold or a conductive paste, atop each die pad. A contact forming tool may then be utilized to shape the conductive bonding material to form bondable contacts. Each bondable contact preferably has a substantially flat region and a second region projecting above the substantially flat region. The projecting region of the contact may include a wedge-shaped projection that extends above and is bounded by the substantially flat region of the contact. The wedge-shaped projection preferably includes an apex above the substantially flat region and side walls extending between the apex and the substantially flat region of the contact.
The bondable contacts may be shaped or formed using a contact forming tool having a tip end with a substantially flat surface and a depression formed in the substantially flat surface. The depression may be a V-shaped groove extending across the tip end of the tool and having sidewalls that form an acute angle relative to one another. The groove may also have a substantially flat portion near the peak on the V-shape. During a contact shaping step, the tip end of the tool is abutted against the conductive bonding material to form the bondable contacts. The preferred shape of the groove formed in the tip end of the bump forming tool is V-shaped, however, other preferred shapes for the groove includes hemispherical, conical, truncated conical, and pyramidal.
In another embodiment of the present invention, a method of making a microelectronic assembly includes providing a first microelectronic element having a front face and a plurality of bondable contacts on the front face, wherein each bondable contact has a substantially flat region and a second region projecting above the substantially flat region. A second microelectronic element having one or more leads with bond regions is then juxtaposed with the microelectronic element so that the bond regions of the leads overlie the bondable contacts. The bond regions of the leads are then abutted against the projecting regions of the contacts and the bond regions of the leads are bonded to the contacts. During bonding, the projecting regions of the contacts deform the bond regions of the leads. The first and second microelectronic elements can be a semiconductor chip, semiconductor wafer, connection component, or a substrate. In certain preferred embodiments, the first microelectronic element is a semiconductor chip and the second microelectronic element is a connection component.